Many integrated circuits (“ICs”) are made up of millions of interconnected devices, such as transistors, resistors, capacitors, and diodes, on a single chip of semiconductor substrate. Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
An FPGA typically includes configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and other types of logic blocks, such as memories, microprocessors, digital signal processors (DSPs), and the like. The CLBs, IOBs, and other logic blocks are interconnected by a programmable interconnect structure. The CLBs, IOBs, logic blocks, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, logic blocks, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as digital clock managers (DCMs), input/output (I/O) transceivers, boundary scan logic, and the like.
FPGA systems have been developed that use one or more ICs in conjunction with the FPGA as a stacked-die functional unit, often referred to as a stacked-die hybrid IC. The second IC might provide additional memory or logic, such as dedicated logic, and be configured to operate with the FPGA through one or more IOBs. Operation of FPGA systems are often limited by I/O resources and associated factors, such as speed and power consumption.
Modeling the stacked-die hybrid IC is necessary to the development and characterization of circuits configured into the programmable fabric of an FPGA and utilizing the full resources of the additional IC. Among other things, modeling involves characterization of the connecting resources in the second IC to the fabric of the FPGA through the IOBs. Techniques for modeling multi-chip FPGA systems providing higher speed and leaving IOBs available for other functionality are desirable.